The present invention relates to an interface controller which controls communication with a storage device, a method for controlling read access, and an information processing apparatus provided with the interface controller; and more particularly, relates to an interface controller which continuously issues read requests, a method for controlling read access which continuously issues read requests, and an information processing apparatus provided with the interface controller.
Peripheral component interconnect express (referred to as PCI EXPRESS™) is known as an interface which is for connecting two devices. Communication in the PCI EXPRESS™ (e.g., an interface which is for connecting two devices) is to send a packet (read request) which requires memory read and receives read response sent back from the other side device in the case when performing memory access (memory read access) for memory read which reads data stored in a memory with respect to the other side device including the memory. The received read response is stored in a receiving buffer and then sent to an upper system bus.
As a method which is for storing the read response in the receiving buffer and improving performance, there is a method in which a read request issuer (for example, a central processing unit (referred to as CPU), direct memory access (referred to as DMA), or the like) continuously issues in view of a receiving buffer size. In this case, in order not to generate overflow in the receiving buffer which receives the read response, the read request issuer needs to calculate a data sending amount in memory read access on the basis of a sideband signal which acquaints a receiving buffer size and status and to control the data sending amount.
However, when the data sending amount is calculated, a load is generated on the read request issuer. Further, a system bus is required for sending and receiving the sideband signal; and consequently, versatility as a device is reduced (Japanese Patent Application Laid-Open No. 2005-322308).